HDL Engineer

About ConfigAI

ConfigAI is building the compiler that turns ML models into FPGA hardware automatically. We are based in Saarbrucken, backed by the Max Planck Institute for Informatics and Google for Startups, and working on one of the hardest problems at the intersection of machine learning and silicon design.

About the Role

We are looking for an HDL Engineer to design and optimise the hardware building blocks that our compiler generates and assembles. You will write hand-crafted RTL modules in Verilog or VHDL, create testbenches, and work closely with compiler engineers to ensure the generated hardware meets area and timing targets. This is a 15 hrs/week, on-site role in Saarbrucken, open to students and professionals (m/w/d).

Key Responsibilities

• · Design reusable RTL modules (Verilog/VHDL) that the compiler uses as hardware building blocks.
• · Review and improve the HDL templates emitted by the compiler code generation backend.
• · Write testbenches to verify functional correctness of generated hardware modules.
• · Optimise RTL for area, latency and throughput on Xilinx and Intel FPGA families.
• · Collaborate with compiler engineers to define clean interfaces between generated and hand-written HDL.
• · Support FPGA implementation flows: synthesis, place-and-route and timing closure.

Required Skills and Experience

• · Strong proficiency in Verilog or VHDL for RTL design.
• · Experience with FPGA implementation flows: synthesis, place-and-route and timing analysis.
• · Understanding of common digital design patterns: pipelining, FIFOs, state machines and AXI interfaces.
• · Ability to write simulation testbenches and interpret waveform results.
• · Comfortable with Xilinx Vivado or Intel Quartus toolchains.

Preferred Skills — Nice to Have

• · Experience with High-Level Synthesis (HLS) tools such as Xilinx Vitis HLS or Bambu.
• · Familiarity with ML accelerator architectures: systolic arrays, PE arrays or dataflow processors.
• · Knowledge of formal verification or property checking.
• · Background in low-power design or timing-driven optimisation.

Why Join Us

• · Your RTL work directly underpins every model we compile: close to the metal, real impact.
• · Small team: your contributions will have direct, visible impact on the product.
• · Research environment: direct access to expertise at the Max Planck Institute for Informatics.
• · Flexible 15 hrs/week commitment: ideal for students or researchers pursuing parallel work.
• · Claude Max (20x) provided — full AI tooling for your day-to-day work.