Careers at ConfigAI

Build the future of AI hardware.

We're a small team solving a hard problem: turning ML models into FPGA hardware automatically. Based in Saarbrucken, backed by Max Planck Institute for Informatics and Google for Startups.

Open Positions · 3 roles

Compiler Engineer

15 hrs / week On-site · Saarbrucken Part-time · m/w/d

Work on the compiler pipeline that maps ML computation graphs to FPGA primitives: parsing, IR transformations and code generation.

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ML Engineer

15 hrs / week On-site · Saarbrucken Part-time · m/w/d

Bridge the gap between ML model architectures and hardware constraints: quantisation, operator fusion and hardware-aware model optimisation.

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HDL Engineer

15 hrs / week On-site · Saarbrucken Part-time · m/w/d

Design and optimise the HDL templates and RTL modules that the compiler emits. Verilog/VHDL expertise required.

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Ayush Kumar

Point of contact

Ayush Kumar

Co-founder, ConfigAI

ayush@configai.co